> For the complete documentation index, see [llms.txt](https://janehacker1.gitbook.io/dsm-ecu/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://janehacker1.gitbook.io/dsm-ecu/chips/e303-m60011.md).

# IC E303 (M60011)

I/O Port Expander

## About

I/O Port Expander/Address latch?

44-pin PLCC

Paired to MH6111

## Photo

![](https://3794348124-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MbMmcGjBEeIX30liMDB%2F-Mc4frsU28GqvkyuskyX%2F-Mc4mRY61n2s5dDLmwsN%2FM60011-E303.JPG?alt=media\&token=fda84f76-0a28-489a-96c9-60cd9c476ed1)

## Tracing pins to EPROM and CPU

{% hint style="warning" %}
This is still in the early discovery phase
{% endhint %}

![](https://3794348124-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2F-MbMmcGjBEeIX30liMDB%2Fuploads%2FmwHwN0dKzMRhQITNzylu%2Frect62034.png?alt=media\&token=b91b0662-f229-41d3-b85c-d188f1492a01)

![Upper left: 27C256 EPROM; Lower left: 76C75T CPU; Right: E303 I/O Port expander](https://3794348124-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MbMmcGjBEeIX30liMDB%2F-Mbh25mQiFKaFxOxrib4%2F-Mbl3wEMesLl8vFWqtf_%2FScreen%20Shot%202021-06-09%20at%2010.00.27%20AM.png?alt=media\&token=e21c47ef-a40c-4af8-85fa-cea0adff1cd3)

```
How is the CPU connected to the EPROM?

27C256 = EPROM IC (DIP-28)
76C75T = CPU IC (PLCC-68)
E303   = I/O Expander (Gate Array) IC (PLCC-44)
E310   = Level Converter IC (PLCC-44)
R22, R23 = Resistors (Surface mount)
RM10X  = Resistor network? (SIP-5)
X      = Not Connected
(E)    = Chip Enable?
(RW)   = Read/Write Enable?
(AS)   = Address Strobe
Q0-7   = Output pins  (EPROM)
AD0-7  = Data pins    (CPU)
A0-13  = Address Pins (EPROM)

CPU to EPROM Connections

27C256 <-> 76C75T
Lbl pin    pin Lbl
Q0  11 <-> 68  AD0 \
Q1  12 <-> 67  AD1  |
Q2  13 <-> 66  AD2  |
Q3  15 <-> 65  AD3   \ Data Lines (Shared)
Q4  16 <-> 64  AD4   /   (0-7)
Q5  17 <-> 63  AD5  |
Q6  18 <-> 62  AD6  |
Q7  19 <-> 61  AD7 /
A8  25 <-> 60  A8  \
A9  24 <-> 59  A9   |
A11 23 <-> 57  A11   > Address Lines
A12 2  <-> 56  A12  |  (8-9, 11-13)
A13 26 <-> 55  A13 /

Eprom to CPU to I/O Expander Connectons

27C256<-->76C75T<-->RM10X<-->E303(M60011)
3(A7)<---------------------->1------------\
4(A6)<---------------------->2             |
5(A5)<---------------------->3             |
6(A4)<---------------------->4              \ Address Lines
7(A3)<---------------------->5              /    (0-7)
8(A2)<---------------------->6             |
9(A1)<---------------------->7             |
10(A0)<--------------------->8------------/
X         1(RW)<------------>23
X         3(E)<-R22--------->20
27C256<-->76C75T<-->RM104<-->E303(M60011)
18(Q6)    62(AD6)   2        12-----------\
17(Q5)    63(AD5)   3        13            |
16(Q4)    64(AD4)   4        14            |
15(Q3)    65(AD3)   5        15             \
27C256<-->76C75T<-->RM103<-->E303(M60011)    > Data (Shared)
13(Q2)    66(AD2)   2        16             /  (0-7)
12(Q1)    67(AD1)   3        17            |
11(Q0)    68(AD0)   4        18            |
19(Q7)    61(AD7)   5        11-----------/
27C256<-->76C75T<-->RM102<-->E303(M60011)
26(A13)   55(A13)   2        25-----------\
X         53(A15)   3        26            > Address Lines
25(A8)    60(A8)    4        24-----------/     (8,13)
X         2(AS)<R23>5<------>21
```

Both the CPU (76C75T) and the I/O port expander (E303) have shared access to all the data lines. The port expander has exclusive access to the first eight address lines (0-7). While the CPU only has access to five address lines (8, 9, 11, 12, 13), two of them (8, 13) are also shared with the port expander. That leaves address lines 9, 11, and 12 to the CPU alone.

Pin 1 on the CPU(RW) connects to pin 23 on the port expander.

Pin 2 on the CPU(AS) connects to pin 21 of the port expander.

Pin 3 on the CPU(E) connects to pin 20 on the port expander.

Pin 53 on the CPU(A15) connects to pin 26 on the port expander.